The present invention is related generally to transistor circuits and, more particularly, to a bias method and circuit for distortion reduction.
Transistor amplifiers and mixers are commonly used building blocks of analog circuits operating at frequencies ranging from audio to radio frequencies (RF). Generally, these circuits are required to minimally distort the signal they operate on to preserve the information carried by the signal.
The signal distortion in active circuits is generated by nonlinearities of the transistor. Consider a simple common-source NMOS amplifier and its equivalent circuit shown in FIGS. 1A and 1B, respectively. In FIG. 1A, M1 is an NMOS transistor, C is a direct current (DC) blocking capacitor, and RL is a drain bias resistor. The equivalent circuit of FIG. 1B is an ideal model of the circuit of FIG. 1A. In FIG. 1B, VGS is the gate-source voltage and ID is the drain current of M1. The drain current ID is a function of VGS. For proper operation, the gate of the transistor M1 should be biased above the threshold voltage to allow a nonzero DC drain current to flow through M1. The gate
A commonly used prior-art bias circuit is shown in FIG. 2 where a transistor M2 is a scaled version (replica) of the transistor M1 with the same gate length but a narrower width. Also shown in FIG. 2 is a reference current source, IREF, and a bias resistor, RB, that isolates the bias circuit from the amplifier input at the operating frequency of the amplifier. The drain of the transistor M1 is biased in the saturation region for high gain. Ideally, the transistor M1 operates as a linear voltage-controlled current source having the following characteristics:
ID=gm(VGSxe2x88x92VTH)xe2x80x83xe2x80x83(1)
where VTH is the threshold voltage of the transistor M1 and gm is the bias-independent coefficient called transconductance in units amperes per volt (A/V).
For further analysis, it is convenient to separate the DC values of ID and VGS from their alternating current (AC) values using the following relations:
ID=ID0+iD
VGS=VGS0+vGS
ID0=gm(VGS0xe2x88x92VTH).xe2x80x83xe2x80x83(2)
where ID0 is the DC drain current and VGS0 is the DC gate-source voltage of M1 generated by the bias circuit. In equation (2) vGS is the AC gate-source voltage equal to the input signal voltage (vIN) and iD is the AC drain current. Equation (1) can be written in terms of the introduced AC values as follows:
iD=gmvGSxe2x80x83xe2x80x83(3)
Where all terms have been previously defined.
When the AC input signal vIN is applied to the circuit, the transistor M1 generates an output AC current equal to gmvIN that creates a voltage drop across the drain-bias resistor RL equal to xe2x88x92gmvINRL. This voltage across the drain-bias resistor RL is the output signal of the amplifier and xe2x88x92gmRL is its gain.
In the ideal amplifier illustrated in FIGS. 1A and 1B, the output signal is a scaled version of the input signal (i.e., there are no spurious responses of the system). The spectrum of the output signal has the same frequency components as the input signal.
Unfortunately, the transconductance of a real-life transistor is not a constant but a function of the input bias voltage. This function is often described by a sophisticated equation or a system of equations. To simplify circuit analysis, this function is replaced by its Taylor series expansion near VGS0 as follows:
gm=g1+g2vGS+g3vGS2+xe2x80x83xe2x80x83(4a)
where g1, g2 and g3 are the expansion coefficients equal to:                                                                                           g                  1                                ⁡                                  (                                      V                    GS                                    )                                            =                                                ⅆ                                      I                    D                                                                    ⅆ                                      V                    GS                                                                                                                                                            g                  2                                ⁡                                  (                                      V                    GS                                    )                                            =                                                                    1                    2                                    ⁢                                                                                    ⅆ                        2                                            ⁢                                              I                        D                                                                                    ⅆ                                              V                        GS                        2                                                                                            =                                                                            1                      2                                        ⁢                                          ⅆ                                              ⅆ                                                  V                          GS                                                                                      ⁢                                          (                                                                        ⅆ                                                      I                            D                                                                                                    ⅆ                                                      V                            GS                                                                                              )                                                        =                                                            1                      2                                        ⁢                                                                  ⅆ                                                                              g                            1                                                    ⁡                                                      (                                                          V                              GS                                                        )                                                                                                                      ⅆ                                                  V                          GS                                                                                                                                                                                                                              g                  3                                ⁡                                  (                                      V                    GS                                    )                                            =                                                                    1                    6                                    ⁢                                                                                    ⅆ                        3                                            ⁢                                              I                        D                                                                                    ⅆ                                              V                        GS                        3                                                                                            =                                                      1                    3                                    ⁢                                                            ⅆ                                                                        g                          2                                                ⁡                                                  (                                                      V                            GS                                                    )                                                                                                            ⅆ                                              V                        GS                                                                                                                                                    (4b)            
Substituting this gm expansion into equation (3) above, we get the following expression for the output current of a real-life NMOS transistor:
xe2x80x83iD=g1vGS+g2vGS2+g3vGS3+xe2x80x83xe2x80x83(5)
This expansion is often called a power series. The first term in the series is called a linear term and represents the desired function of the transistor (e.g., the transistor M1). The second term is called the 2nd-order nonlinearity. The third term is called the 3rd-order nonlinearity, etc. The nonlinearities are not desirable since they generate spurious responses that interfere with the desired signal.
There are several well known techniques to reduce the circuit spurious responses relative to its desired fundamental response. These techniques are often referred to as the linearization techniques. The simplest and widely-used technique is based on the fact that the 2nd and 3rd-order expansion coefficients of the FET output current, g2 and g3, decrease relative to the linear transconductance g1 at gate-to-source voltages much larger than the threshold voltage. So, selecting large-enough VGS0 results in much smaller spurious responses relative to the fundamental response of the circuit. Unfortunately, this technique increases the DC current consumption of the circuit which may not be acceptable for some applications (e.g., battery operated devices).
Another technique is based on the fact that, for many field-effect transistors, there are particular input bias voltages at which either the 2nd or the 3rd-order expansion coefficient is zero. These bias voltages are typically close to the threshold voltage and, therefore, don""t result in a large DC drain current. If a transistor is biased at such a voltage, theoretically it generates zero 2nd or 3rd order distortion. It is possible to calculate a bias voltage at which g2 or g3 is zero from the simulated or measured transfer characteristic of the transistor. The calculated bias voltage will only be optimum for either a typical transistor for which the model was extracted or the measured transistor-sample. It will also be optimum only at a specific temperature at which the transfer characteristic was simulated or measured. It possible to design a bias circuit that generates this calculated gate-to-source voltage at which g2 or g3 is zero using a resistive divider for example. However, it will not satisfactorily eliminate the corresponding distortion as the operating temperature changes or the parameters of the transistor manufacturing process drift.
Accordingly, it can be appreciated that there is a significant need for a bias circuit that eliminates undesirable distortion components independent of temperature fluctuations and manufacturing process drifts. The present invention provides this, and other advantages, as will be apparent from the following detailed description and the accompanying figures.
The present invention is embodied in a method and circuit for biasing a transistor. The transistor to be biased has a transfer characteristic that may be characterized by a linear or first-order term that describes a straight line and nonlinear or higher-order terms, such as 2nd-order and 3rd-order nonlinearities, that describe the deviations of the transfer characteristic from the straight line. The inventive method generates a direct current signal proportional to a selected nonlinearity of the transistor and uses the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero.
In one example, the selected nonlinearity is a 2nd-order nonlinearity and the DC signal comprises first, second and third portions. The first, second and third portions are combined to form the DC signal. In another example, the selected nonlinearity is a 3rd-order nonlinearity and the DC signal comprises first, second, third and fourth portions. The first, second, third and fourth portions are combined to form the DC signal.
The method may also include providing a mirror to bias circuit elements that generate the DC signal. A feedback circuit may also be provided to sense the DC signal and generate the bias voltage at which the DC signal and the selected nonlinearity are zero. The DC signal may be a current or a voltage, single-ended or differential.
The response of the transistor may be characterized by a power series having a linear term and nonlinear terms or nonlinearities. The nonlinearities each consist of multiple components. The bias circuit may comprise individual bias transistors designed to generate DC signal portions corresponding to the individual components of a selected nonlinearity. The DC signal portions are combined to form the DC signal proportional to the selected nonlinearity. A feedback circuit may be provided to sense the DC signal and generate the bias voltages of the bias transistors at which the DC signal and the selected nonlinearity are zero. For example, a 2nd-order nonlinearity may be characterized by first, second and third components. The bias circuit may comprise first, second and third bias transistors that produce DC signal portions corresponding to the first, second and third components. The DC signal portions are combined to generate the DC signal proportional to the 2nd-order nonlinearity. A feedback circuit senses the DC signal and generates the bias voltages of the bias transistors at which the DC signal is zero. One of these voltages is applied to the main transistor effectively canceling its 2nd-order nonlinearity.